1. Field of the Invention
The present invention relates to a high-speed pipelined ARIA encryption apparatus, and more particularly, to a high-speed pipelined ARIA encryption apparatus in which a plurality of round units are provided in accordance with the number of times of rounds so that ARIA encryption can be performed at high speed.
2. Discussion of the Related Art
An ARIA encryption algorithm is a public-private block symmetrical key encryption algorithm developed by the NSRI.
In general, in the ARIA encryption algorithm, with respect to the number of rounds and the size of a master key, it is recommended to use a 12-round operation when the master key has 128 bits, to use a 14-round operation when the master key has 192 bits, and to use a 16-round operation when the master key has 256 bits.
The ARIA algorithm performs an encryption operation by round operations that include a substitution operation and a diffusion operation.
In the ARIA algorithm, key extension processes include key initialization processes and round key generation processes of generating four 128-bit initialization key values W0, W1, W2, and W3 when the master key MK and specific initialization constants (CK1, CK2, and CK3) are given as inputs.
In accordance with a method of performing the substitution and diffusion operations and a method of performing the key extension processes, there is a difference in the time spent on the ARIA encryption operation and used hardware resources, which is directly connected to the performance of an ARIA encryption processor.
The conventional ARIA encryption apparatus repeatedly drives one round unit so that a plurality of clock cycles are used for encrypting a large amount of data when the encryption operation is performed.